The present invention relates to a wide aspect ratio television receiver including a display having an aspect ratio of 16:9, and in particular, to a television signal processor capable of displaying video signals having different aspect ratios on the display.
Recently, attention has been given to broadcasting of video signals having an aspect ratio 16:9, such as for example in the high definition television system and a second-generation EDTV system, which are different from television systems conforming to the conventional National Television System Committee (NTSC).
However, since the present NTSC television system is widely used throughout the world, in order for the broadcasting system of a high picture quality such as the high definition television broadcasting or the second-generation EDTV systems to be widely used throughout the world, the NTSC image of the standard ratio 4:3 is required to be displayed with the aspect ratio 16:9 of the newer TV systems for establishing compatibility therebetween.
An example of displaying an image the aspect ratio 4:3 on a display of the aspect ratio 16:9 has been described in the JP-A-1-194784. FIG. 2 shows a block diagram of the overall configuration of a circuit system described in the JP-A-1-194784.
FIG. 2 includes an input terminal 201 for receiving a video signal, a Y/C separating circuit 202, a line memory 203, a wide display 204, a synchronizing signal reproducing circuit 205, a write control PLL circuit 206, a read control PLL circuit 207, and a variable vertical deflection circuit 208.
A video input signal supplied from the input terminal 201 is separated by the Y/C separating circuit 202 into a luminance signal and color difference signal, which are then subjected to a time-axis compression in the horizontal direction so as to be presented on the wide display 204. In addition, the synchronizing signal (sync) reproducing circuit 205 separates a synchronizing signal from the video input signal. In response to the synchronizing signal, the write control PLL circuit 206 generates clock and control signals associated with a write operation of the line memory 203 and the read control PLL circuit 207 generates clock and control signals associated with a read operation of the line memory 203. Moreover, the sync reproducing circuit 205 supplies the synchronizing signal also to the variable vertical deflection circuit 208 which drives the wide display 204.
The circuit of FIG. 2 has the following features.
1) The line memory 203 stores video signals received in one-horizontal period (lH) such that using a write clock reproduced by the write control PLL circuit 206 from the signal outputted from the sync reproducing circuit 205 and a read clock which is produced by the read control PLL circuit 207 and which has a frequency equal to 4/3 of the frequency of the write clock, a time compression in a horizontal direction is developed.
2) In the wide display 204, the vertical deflection can be variably achieved so as to support a function of an expansion and magnification in the vertical direction.
With the features above, images respectively having aspect ratios 16:9 and 4:3 can be presented on a display of an aspect ratio 16:9.
However, when video input signals include signals associated with different screen display areas employed in the current broadcasting systems and film software systems of the CineScope and Vista sizes, an advantageous feature is achieved that the film software images can be displayed fully on the screen and the signal of an aspect ratio 4:3 can be presented in a desired position of the screen having an aspect ratio 16:9.
However, in the prior art described above, when the input signal contains a large amount of jitter components like in a VTR signal, the vertical lines of the screen appear in as twisted or distorted images. Moreover interpolation between scanning lines is not taken into consideration during image magnification in the vertical direction which caused the following problems.
1) A phase-locked loop (PLL) is required for clock generation on a signal processing side and a PLL is required for a synchronization signal reproduction on the display side. These PLLs respond differently to a synchronization deviation causing responses such as a jitter and a skew which cannot be completely eliminated.
2) A vertical magnification function achieved by changing the vertical deflection of the display expands the interval between the scanning lines to accomplish the vertical magnification. Consequently, the scanning line structure becomes to much more visible. In addition, it is necessary to additionally dispose a change-over signal for a change-over to a deflection driver of the display or the like.